(1) Field of the Invention
The present invention relates to a process used to fabricate semiconductor devices, and more specifically to a dry etching procedure, used to form an insulator shape with a tapered profile.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve device performance, while still attempting to reduce the manufacturing cost of specific metal oxide semiconductor field effect transistor, (MOSFET), devices. The ability to create MOSFET devices with sub-micron features, or micro-miniaturization, has allowed these objectives to be realized. Devices with sub-micron features exhibit less performance degrading resistances and capacitances, thus improving device performance. In addition devices with sub-micron features, allow smaller semiconductor chips to be obtained, still possessing equal, or greater, circuit densities than counterparts, fabricated using larger features. The use of smaller chips allow a greater number of chips to be realized from a specific size starting semiconductor substrate, thus reducing the manufacturing cost of a specific chip.
The realization of semiconductor devices, with sub-micron features, has been mainly attributed to advances in specific semiconductor fabrication disciplines, used in the manufacture of sub-micron MOSFET devices, such as photolithography and dry etching. The use of more advanced exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron features to be routinely obtained in photoresist layers. In addition the development of advanced dry etching tools and procedures, have allowed the sub-micron images in overlying photoresist layers, to be successfully transferred to underlying materials, used in the manufacture of sub-micron MOSFET devices. However for specific cases, a specific shape or profile, in a material used for the sub-micron MOSFET device, is desired. Therefore for specific applications, specific dry etching procedures are needed for successful fabrication of the sub-micron MOSFET device.
For example in the process used to create insulator filled shallow trenches, a dry etch procedure is initially used to remove excess insulator from regions external to the shallow trench, prior to a final chemical mechanical polishing procedure, used to leave planarized insulator material only in the shallow trench. If the dry etch process is performed without protecting the insulator in the shallow trench, the insulator in the shallow trench may be removed. For this case a photoresist shape is used to mask a region of insulator directly over the insulator filled shallow trench, to protect this region during a dry etching procedure. Two critical aspects of the dry etching procedure are the ability to align the protecting photoresist shape, directly over the shallow trench, and the selectivity of the dry etching procedure, or the ability of the dry etching procedures to stop on the material underlying the insulator layer, in regions external to the shallow trench. This invention will describe a process in which a tapered, or sloped insulator profile, is obtained, thus reducing the critical photoresist alignment requirement. In addition this invention will offer a dry etch chemistry, with selectivity between overlying insulator, silicon oxide in this case, and underlying silicon nitride, allowing complete insulator removal with a minimal attack of underlying silicon nitride. Prior art, such as Hijikata, et al, U.S. Pat. No. 5,254,214, describe a method of plasma taper etching, however that invention does not offer the detailed process needed to create the tapered profile needed in this invention.